The PCI BUS has _____ interrupt request lines.

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The PCI BUS has _____ interrupt request lines.

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Posted Date:-2021-03-14 23:10:46

More MCQS Questions and answers

  1. The serial port is used to connect basically _____ and processor
  2. ____ address space gives the PCI its plug and plays capability.
  3. ____ provides a separate physical connection to the memory.
  4. ____ signal is sent by the initiator to indicate the duration of the transaction.
  5. _____ is used as an intermediate to extend the processor BUS.
  6. _____ to increase the flexibility of the serial ports.
  7. _____ to increase the flexibility of the serial ports.
  8. _______ is an extension of the processor BUS.
  9. A complete transfer operation over the BUS, involving the address and a burst of data is called _____
  10.  IDE disk is connected to the PCI BUS using ______ interface.
  11.  In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel port interface.
  12.  In a serial port interface, the INTR line is connected to _____
  13.  In the output interface of the parallel port, along with the valid signal ______ is also sent.
  14.  The disadvantage of using a parallel mode of communication is ______
  15.  The double buffer is used for _________
  16.  The key feature of the PCI BUS is _________
  17.  The key feature of UART is _________
  18.  The mode of transmission of data, where one bit is sent for each clock cycle is ______
  19.  The standard used in serial ports to facilitate communication is _____
  20.  The Status flag circuit is implemented using _____
  21.  Which most popular input device is used today for interactive processing and for the one line entry of data for batch processing?
  22. DDR stands for __________
  23.  The Interface circuits generate the appropriate timing signals required by the BUS control scheme.
  24. IDE stands for _________
  25. In a general 8-bit parallel interface, the INTR line is connected to _______
  26. In a serial port interface, the INTR line is connected to _____
  27. IRDY# signal is used for _______
  28. ISO stands for __________
  29. PCI stands for _______
  30. SCSI stands for ___________
  31. The _____ circuit enables the generation of the ASCII code when the key is pressed.
  32. The ______ is the BUS used in Macintosh PC’s.
  33. The best mode of connection between devices which need to send or receive large amounts of data over a short distance is _____
  34. The data transfer in UART is done in ______
  35. The device connected to the BUS are given addresses of ____ bit.
  36. The double buffer is used for _________
  37. The key feature of UART is _________
  38. The master is also called as _____ in PCI terminology.
  39. The mode of transmission of data, where one bit is sent for each clock cycle is ______
  40. The output of the encoder circuit is/are ______
  41. The PCI BUS has _____ interrupt request lines.
  42. The PCI BUS supports _____ address space/s.
  43. The PCI follows a set of standards primarily used in _____ PC’s.
  44. The serial port is used to connect basically _____ and processor.
  45. The standard used in serial ports to facilitate communication is _____
  46. The status flags required for data transfer is present in _____
  47. The system developed by IBM with ISA architecture is ______
  48. The transformation between the Parallel and serial ports is done with the help of ______
  49. The transformation between the Parallel and serial ports is done with the help of ______
  50. The use of spooler programs or _______ Hardware allows PC operators to do the processing work at the same time a printing operation is in progress.
  51. The video devices are connected to ______ BUS.
  52. To overcome multiple signals being generated upon a single press of the button, we make use of ______
  53. UART stands for ________
  54. UART stands for ________
  55. User programmable terminals that combine VDT hardware with built-in microprocessor is _____
  56. What is the full form of ANSI?
  57. What is the full form of ISA?
  58. When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave.
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