A multilevel page table is preferred in comparison to a single level page table for translating virtual address to physical address because ________

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A multilevel page table is preferred in comparison to a single level page table for translating virtual address to physical address because ________

1.it reduces the memory access time to read or write a memory location

2. it helps to reduce the size of page table needed to implement the virtual address space of a process

3.it is required by the translation lookaside buffer

4.it helps to reduce the number of page faults in page replacement algorithms

Posted Date:-2022-03-26 09:25:13

More MCQS Questions and answers

  1. In segmentation, each address is specified by _______
  2. Logical memory is broken into blocks of the same size called _________
  3. The relocation register helps in _______
  4. To obtain better memory utilization, dynamic loading is used. With dynamic loading, a routine is not loaded until it is called. For implementing dynamic loading _______
  5. A multilevel page table is preferred in comparison to a single level page table for translating virtual address to physical address because ________
  6. An ______ uniquely identifies processes and is used to provide address space protection for that process.
  7. Consider a computer with 8 Mbytes of main memory and a 128K cache. The cache block size is 4 K. It uses a direct mapping scheme for cache management. How many different main memory blocks can map onto a given physical cache block?
  8. Each entry in a segment table has a _______
  9. Each entry in a translation lookaside buffer (TLB) consists of ______
  10. Every address generated by the CPU is divided into two parts. They are _______
  11. For every process there is a __________
  12. For larger page tables, they are kept in main memory and a ____ points to the page table.
  13. If a page number is not found in the TLB, then it is known as a ______
  14. If the offset is legal _______
  15. If the size of logical address space is 2 to the power of m, and a page size is 2 to the power of n addressing units, then the high order _____ bits of a logical address designate the page number, and the ____ low order bits designate the page offset.
  16. If there are 32 segments, each of size 1Kb, then the logical address should have ______
  17. Illegal addresses are trapped using the _____ bit.
  18. In a paged memory, the page hit ratio is 0.35. The required to access a page in secondary memory is equal to 100 ns. The time required to access a page in primary memory is 10 ns. The average time required to access a page is?
  19. In contiguous memory allocation ______
  20. In fixed size partition, the degree of multiprogramming is bounded by _______
  21. In paged memory systems, if the page size is increased, then the internal fragmentation generally _____
  22. In paging the user provides only ________ which is partitioned by the hardware into ________ and ______
  23. Memory protection in a paged environment is accomplished by _______
  24. Operating System maintains the page table for _______
  25. Paging increases the ______ time.
  26. Physical memory is broken into fixed-sized blocks called _____
  27. Program always deals with _________
  28. Smaller page tables are implemented as a set of _______
  29. The ___ is used as an index into the page table.
  30. The _____ table contains the base address of each page in physical memory.
  31. The address of a page table in memory is pointed by ______
  32. The first fit, best fit and worst fit are strategies to select a ______
  33. The offset ‘d’ of the logical address must be ______
  34. The page table contains _______
  35. The page table registers should be built with _______
  36. The percentage of times a page number is found in the TLB is known as ______
  37. The protection bit is 0/1 based on _____
  38. The segment base contains the ______
  39. The segment limit contains the _______
  40. The size of a page is typically _________
  41. Time taken in memory access through PTBR is ______
  42. Transient operating system code is code that ______
  43. What is compaction?
  44. What is the operating system?
  45. When memory is divided into several fixed sized partitions, each partition may contain ________
  46. When the entries in the segment tables of two different processes point to the same physical location ______
  47. When the valid – invalid bit is set to valid, it means that the associated page ______
  48. When there is a large logical address space, the best way of paging would be ______
  49. With paging there is no ________ fragmentation.
  50. With relocation and limit registers, each logical address must be _______ the limit register.
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