VHDL MCQ Quiz Hub

1. Which of the following is the correct use of the signal?
To set a default value
To pass value between circuits
To declare a variable
To represent local information

2. What is the use of a variable?
To represent local value
To represent default value
To set default value
To declare a subprogram

3. Use of constants is to _________
Represent wires
Represent local information
Represent default value
Pass value between entities

4. How to declare a constant in VHDL?
CONSTANT name : type := value;
CONSTANT name := value;
CONSTANT name := type := value;
CONSTANT name := type : value;

5. Which of the following is local to the block in which it is declared?
Signal
Integer
Constant
Variable

6. A constant is declared in Architecture, it will be accessible in ________
Whole code
Within the same architecture
In the entity associated and corresponding architecture
In the process within the architecture

7. Which of the following can’t be declared in an architecture?
Signal
Constant
Variable
BIT_VECTOR

8. What is the scope of a constant declared in an entity?
Local to the entity
Global to the whole code
Local to the port
Global to the entity and all the architecture associated

9. A user wants a constant to be declared in such a way that it can be accessible by whole code, where should the user declare this constant?
Package
Entity
Architecture
Configuration

10. What is the full form of VHDL?
Verilog Hardware Description Language
Very High speed Description Language
Variable Hardware Description Language
Very high speed Hardware Description Language

11. What is the basic use of EDA tools?
Communication of Electronic devices
Fabrication of Electronics hardware
Electronic circuits simulation and synthesis
Industrial automation

12. After compiling VHDL code with any EDA tool, we get __________
Final device
FPGA
Optimized netlist
Netlist

13. Which of the following is not an EDA tool?
Visual C++
Quartus II
Xilinx ISE
MaxPlus II

14. The process of transforming a design entry information of the circuit into a set of logic equations in any EDA tool is known as _________
Simulation
Synthesis
Optimization
Verification

15. An Antifuse programming technology is associated with _________
CPLDs
FPGAs
SPLDs
ASICs

16. Which of the following is not a back end EDA tool?
Floor planning tools
Placement tools
Routing tools
Simulators

17. What are the differences between simulation tools and synthesis tool?
Simulators are used to check the performance of circuit and Synthesis tools are for the fabrication of circuits
Simulators and Synthesis tools works exactly same
Simulators are used just to check basic functionality of the circuit and Synthesis tools includes timing constraints and other factors along with simulation
Simulation finds the error in the code and Synthesis tool corrects the code

18. What is the extension of the netlist file; input to the place and route EDA tools?
EIDF
SDF
TXT
CPP

19. n what aspect, HDLs differ from other computer programming languages?
No aspect; both are same
HDLs describe hardware rather than executing a program on a computer
HDLs describe software and not hardware
Other computer programming languages have more complexity

20. Which of the following HDLs are IEEE standards?
VHDL and Verilog
C and C++
Altera and Xilinx
Quartus II and MaxPlus II

21. Why we needed HDLs while having many traditional Programming languages?
Traditional programming languages are complex
HDLs are complementary to traditional programming languages to complete the design process
Some characteristics of digital hardware couldn’t be captured by traditional languages
HDLs offer more complexity than traditional programming languages.

22. Why do we need concurrent processing for describing digital systems in HDLs?
Faster processing than conventional programming languages
Concurrent processing is easier than sequential processing
It allows taking timing constraints into consideration
Complexity of digital systems needs concurrent processing

23. VHDL is based on which of the following programming languages?
ADA programming language
C
Assembly
PHP

24. What is the advantage of using VHDL instead of any other HDL?
Week typing
Based on ADA
Portability
Easy to code

25. Which of the following is a characteristic of VHDL?
Case sensitive
Use of simple data types
Based on C programming language
Strongly typed language

26. Which of the following is a characteristic of Verilog HDL?
Strongly typed language
Case sensitive
Better library
Not portable

27. Which of the following is used at the end of a statement?
; (Semicolon)
— ( double hyphen)
_ (underscore)
No sign is used at the end of statement

28. Which of the following is used at the end of a statement?
; (Semicolon)
— ( double hyphen)
_ (underscore)
No sign is used at the end of statement

29. Which of the following is not defined by the entity?
Direction of any signal
Names of signal
Different ports
Behavior of the signals

30. Which of the following can be the name of an entity?
NAND
Nand_gate
Nand gate
AND

31. Which of the following mode of the signal is bidirectional?
IN
OUT
INOUT
BUFFER

32. In an assignment statement, OUT signal can be used only to the ___________
Left of <= operator
Right of <= operator
Any side of <= operator
Right of := operator

33. On which side of assignment operator, we can use the IN type signal?
Left
Right
Both
Can’t be used

34. What is the difference between OUT and BUFFER?
BUFFER can’t be used inside the entity for reading the value and OUT can be
BUFFER can only be read whereas OUT can only be assigned a value c)
BUFFER can be read as well as assigned a value but OUT can only be assigned
Both are same

35. What is the difference between OUT and BUFFER?
BUFFER can’t be used inside the entity for reading the value and OU can be
BUFFER can only be read whereas OUT can only be assigned a value c) BUFFER can be read as well as assigned a value but OUT can only be assigned
Both are same
Both are same

36. How to control the structure and timing of the entity can be changed?
By using TIME variable in the entity
By changing the entity declaration from time to time
By using some special code
By using GENERICS

37. Which of the following is the default mode for a port variable?
IN
OUT
INOUT
BUFFER