VHDL MCQ Quiz Hub

1. What does modeling type refer to?
Type of ports in entity block of VHDL code
Type of description statements in architecture block of VHDL code
Type of data objects
Type of Signals

2. Which of the following is not a type of VHDL modeling?
Behavioral modeling
Dataflow modeling
Structural modeling
Component modeling

3. In behavioral modeling, what do descriptive statements describe?
How the system performs on given input values
How e design is to be implemented
Netlist
Concurrent execution

4. In behavioral modeling, what do descriptive statements describe?
How the system performs on given input values
How e design is to be implemented
Netlist
Concurrent execution

5. Which of the following statement is used in structural modeling?
portmap()
process()
if-else
case

6. What is the basic unit of behavioral description?
Structure
Sequence
Process
Dataflow

7. Which of the following modeling style follows the sequential processing of instructions?
Dataflow modeling
Behavior modeling
Structural modeling
Component modeling

8. _________ modeling uses logic gates and basic blocks to describe the functionality of system.
Behavioral
Structural
Dataflow
Component

9. Which of the following architecture defines the data flow modeling of ‘and’ gate?
ARCHITECTURE and_1 OF and_gate IS begin y <= a AND b; end and_1;
ARCHITECTURE dataflow OF and_gate IS Process(a, b, y); begin y <= a AND b; end dataflow;
ARCHITECTURE and_1 OF and_gate IS begin IF(a = ‘1’ and b = ‘1’) THEN c <= 1; ELSE c <= ‘0’; end and_1;
ARCHITECTURE dataflow OF and_gate IS begin y <= a AND b; end and_1;

10. Refer to the code given below, which type of modeling is used to describe the system? ARCHITECTURE and_1 OF and_gate IS begin process(a, b, y) begin IF(a = ‘1’ and b = ‘1’) THEN y <= ‘1’; ELSE y <=’0’; end IF; END process; END and_1;
Structural
Component
Dataflow
Behavioral

11. Which logic function is described in the code given below? ARCHITECTURE my_func OF my_logic IS begin process(a, b, y) begin IF(a = ‘0’ and b = ‘0’) THEN y <= ‘0’; ELSIF (a = ‘1’ and b= ‘1’) THEN y<= ‘0’; ELSE y <= ‘1’; END if; END process; END my_func;
AND
EXOR
OR
EXNOR

12. Which modeling style does the following code represents? Architecture my_logic OF logic_func IS Component gate_1 PORT (b1, b2 : IN BIT; s : OUT BIT); END component; Component gate_2 IS PORT (b1,b2 : IN BIT; C : OUT BIT); END component; SIGNAL a, b, sum, carry : BIT; begin EXOR : gate_1 portmap (a, b, sum); AND : gate_2 portmap (a,b ,carry); END my_logic
Structural
Component
Behavior
Dataflow

13. Ports are known as _________ to the component.
Structure
Behavior
Function
Interface

14. What is the use of a function called port map()?
Component declaration
Defining identifiers
Component instantiation
Defining inputs and outputs

15. The signal assignment is considered as a ________
Concurrent statement
Sequential statement
Subprogram
Package declaration statement

16. How can we use an assignment statement as a sequential assignment?
By using keyword WAIT
By using a delay mechanism
By using conditional statements
By using it in any process

17. The sequential assignment statement is activated, whenever ________
The waveform associated changes its value
The process is terminated
The execution is scheduled
The value of the target is needed

18. The concurrent assignment statement is activated whenever ______
The execution is scheduled
The value of the target is needed
The waveform associated changes its value
The process is terminated

19. The concurrent assignment statement is activated whenever ______
The execution is scheduled
The value of the target is needed
The waveform associated changes its value
The process is terminated

20. Which of the following is correct syntax for a signal assignment statement (if {} specifies an optional part)?
target <= {delay_mechanism} waveform;
target <= delay_mechanism waveform;
target <= delay_mechanism {waveform};
target <= {delay_mechanism} {waveform} value;

21. The conditional assignment statement is a _________ assignment.
Sequential
Concurrent
Selected
None of the above

22. The conditional assignment statement is a _________ assignment.
Sequential
Concurrent
Selected
None of the above

23. Delays are generally ignored in ________ assignments statements.
Concurrent
Conditional
Sequential
Selected

24. Which of the following can’t be a mode for target operand of assignment statement?
BUFFER
INOUT
OUT
IN

25. Which of the following is a variable assignment statement?
<=
:=
=>
==

26. Which of the following is a keyword used for conditional assignment?
IF
WHEN
FOR
END

27. For a signal used in sequential assignment, it can have _______
1
2
3
4

28. The selected concurrent statement is equivalent to ________ sequential statement.
If else
Loop
Wait
Case

29. Those statement which are placed under ________ are concurrent.
Process
Function
Architecture
Procedure

30. Process is a _______ statement.
Concurrent
Sequential
Delay
Both concurrent and sequential

31. If there is more than one process in a VHDL code, How they are executed?
One after the other
Concurrently
According to sensitivity list
Sequentially

32. Local variables in a process can be declared __________
Anywhere within the process
After a sequential statement
Before the BEGIN keyword
After the BEGIN keyword

33. Sensitivity list of a process contains __________
Constants
Signals
Variables
Literals

34. Which of the following statement is used when there are no signals in the sensitive list?
WHEN
IF ELSE
WAIT
CASE

35. What is the effect of the sensitivity list on the process?
Process executes when any of the signal in sensitivity list changes
Process executes sequentially when sensitivity list is specified
If there is no sensitivity list, then the process will not execute
Helps in simulation

36. If no signal in the sensitivity list is changed, then how many times the process will be executed?
3
2
1
0

37. Which of the following statements can be seen as sequential equivalent to the selected concurrent assignment?
IF ELSE
WAIT
WHEN
CASE

38. A __________ can’t be declared inside a process.
Signal
Variable
Constants
Subprograms

39. The process can be __________ by using WAIT statements.
Suspended
Resumed
Suspended as well as resumed
Cannot be determined

40. A postponed process runs when ___________
All the other processes have completed
After completion of one particular process
Concurrently with all other processes
First of all processes

41. Which of the following statement can’t be used inside a process?
WAIT
IF ELSE
Variable declaration
PORT MAP

42. The value of y is initially 1 and it is changed after one delta cycle to 0. How many delta cycles (starting from the beginning) will be taken to change the initial value of z, refer to the process given below? PROCESS (y) BEGIN x <=y; z <= NOT y; END PROCESS
1
2
3
4

43. A combinational process must have all the _________ signals in its sensitivity list.
Input
Output
Declared
Used

44. Which of the following circuit can’t be described without using a process statement?
Multiplexer
D flip-flop
Decoder
Comparator

45. Which of the following signal uses keyword EVENT?
Variables
Output
Input
Clock

46. Refer to the code given below, what kind of circuit is designed? SIGNAL x : IN BIT; SIGNAL y : OUT BIT; SIGNAL clk : IN BIT; PROCESS (clk) BEGIN IF (clk’EVENT and clk = ‘1’) y ;&lt= x; END PROCESS
Buffer
Latch
Flip flop
Shift Register

47. The driver(s) of signal y is _________ PROCESS () BEGIN y <= ‘1’; y <= x; y <= z; END PROCESS;
z
x
x and z
1

48. The resolution function is needed to resolve the value of _______ PROCESS () BEGIN y <= x; y <= z; END PROCESS;
z
y
x
No x, y and z

49. What kind of statement is the IF statement?
Concurrent
Sequential
Assignment
Selected assignment

50. Which of the following keyword is not associated with IF statement?
ELSE
THEN
ELSIF
WHEN

51. Which of the following represents the correct order for keywords?
IF, THEN, ELSIF, THEN, ELSE
IF, ELSE, THEN, ELSIF, THEN
IF, ELSIF, THEN, ELSE, THEN
IF, THEN, ELSE, THEN, ELSIF

52. If the condition of IF statement is an expression, then what should be the type of the result of the expression?
Bit
Std_logic
Boolean
Integer

53. In the following lines, what should be the value of signal y, if a and b both are at logic high? PROCESS (a, b) BEGIN IF( a XOR b <=’1’) y <= ‘1’; ELSIF (a AND b <= ‘0’) y <= a; ELSE y <= ‘0’; END IF; END PROCESS;
a
b
0
1

54. Which of the following condition has topmost priority?
IF
ELSIF
ELSE
THEN

55. What logic is described in the following logic? PROCESS (a, b) IF (a = ‘1’ AND b = ‘0’ OR a= ’0’ AND b = ‘1’) THEN y <= ‘1’; ELSIF (a = ‘1’ AND b= ‘1’) THEN y <= ‘0’; ELSE y <= ‘0’; END IF
EXOR
EXNOR
AND
NOR

56. One IF statement can have multiple ___________
IF
ELSIF
ELSE
CASE

57. If a user gets an error at the time of simulation which is “ the IF statement is illegal” what could be the reason?
Using IF statement in architecture body
Using IF statement without ELSE
Using multiple ELSE statements
Using concurrent assignment in the IF

58. In a clocked process, IF statement is used to __________
To run statements sequentially
To use concurrent assignment within process
To detect the clock signal
To implement sequential circuit

59. What will be the output in the following code? ARCHITECTURE my_logic OF my_design IS BEGIN a <= 1; b <= 1; PROCESS (a, b) BEGIN IF (a AND b = 1) THEN output <= a; ELSIF (a OR b = 1) THEN output <= b; ELSE output <= 0; END IF; END PROCESS; END my_logic;
0
1
b
a

60. What is the problem with IF statement?
Overlapping of conditions
No default value
The condition can be Boolean only
Restriction on number of ELSE statement

61. In which of the following statements, all the branches are equal in priority?
IF
CASE
WAIT
LOOP

62. In case any of the conditions is not covered by ‘cases’ in the case statement, which of the following keyword can be used to cover all those conditions?
ELSE
ELSIF
REMAINING
OTHERS

63. CASE is a sequential statement, which is similar to _________ concurrent statement.
Concurrent assignment
PORT MAP
WHEN
THEN

64. What will be the value of Z in the following code? ENTITY case_1 IS Port (a, b, c, y : IN INTEGER range 0 TO 31 z : OUT INTEGER range 0 TO 31) ARCHITECTURE example OF case_1 IS BEGIN y <= 2; a <= 4; b <= 5; c <=6; PROCESS(a, b, c, y) BEGIN CASE y+1 IS WHEN 1 => z <= a; WHEN 2 => z <= b; WHEN 3 => z <= c; WHEN OTHERS => Z <= 0; END CASE; END PROCESS; END example;
2
4
5
6

65. What should be the type of choices in the CASE statement?
Boolean
Integer
Same as expression
No restriction on the type

66. If one wants to perform no action, when any condition is true, then which of the following keyword can be used?
NO OPERATION;
NOP;
NULL;
NEXT

67. It is not possible to use range with _________ types.
Integer
BIT_VECTOR
STD_LOGIC
Natural

68. The CASE statement in VHDL is similar to _________ in C.
Switch
If else
Pointers
Arrays

69. Which of the following operators can’t be used in the choices of a CASE?
Arithmetic
Logical
Relational
Every type of operators can be used

70. What is the main use of a CASE statement?
To design multiplexers
To design Comparators
To design Flip flop
To design state machines

71. Which of the following is most complex?
IF THEN ELSE
Nested IF THEN ELSE
ELSIF
CASE

72. Which of the following is not a legal statement used Ii CASE?
WHEN 1 =>
WHEN 1 TO 3 =>
WHEN 1|3 =>
WHEN 1 THEN

73. A loop statement is used where we needs to ________
Select one from many choices
Check a condition
Repeat the statements
Choose one from two cases

74. Loop is a ________ statement.
Concurrent
Sequential
Assignment
Functional

75. What is the use of FOR loop?
To repeat the statement finite number of times
To repeat the statement until any condition holds true
To repeat the statements for infinite time
To repeat statements inside until any condition is false

76. What is the use of WHILE loop?
To repeat the statement finite number of times
To repeat the statement until any condition holds true
To repeat the statements for infinite time
To repeat statements inside until any condition is false

77. What does the next statement in loops do?
Skips the current iteration
Starts the next loop by ending the current
Exits the loop
Skips the next line of the loop

78. What is the syntax to use the NEXT statement?
NEXT condition loop_label
NEXT loop_label WHEN condition
loop_label NEXT WHEN condition
loop_label NEXT condition

79. The correct syntax for using EXIT in a loop is ___________
EXIT loop_label WHEN condition;
EXIT WHEN condition loop_label;
loop_label WHEN condition EXIT
EXIT WHEN loop_label condition

80. FOR loop uses a loop index, the type of loop index is _________
STD_LOGIC_VECTOR
BIT_VECTOR
INTEGER
REAL

81. Where do we declare the loop index of a FOR LOOP?
Entity
Architecture
Library
It doesn’t have to be declared

82. A FOR loop is inside a WHILE loop. Inside the FOR loop, the EXIT statement is used in such a way that after 4 iterations, it will execute. After the execution of EXIT statement, the control will be passed ________
Outside the FOR loop
Outside the WHILE loop
At the next iteration of WHILE loop
At the next iteration of FOR loop

83. On what side of the assignment statement, one can use a loop index?
Left
Right
Left or Right
Loop index can’t be used in an assignment

84. The FOR loop is not synthesizable if it contains ______ statement. a) d)
WHEN
THEN
WAIT
IF

85. The FOR loop is not synthesizable if it contains ______ statement.
WHEN
THEN
WAIT
IF