R4RIN – MCQs, Mock Tests | VHDL VHDL Mcq

WAIT statement can’t appear under _______ directly.

1. Architecture
2. Process
3. Procedure
4. Subprogram

✅ Correct Answer: 1

Which of the following can’t be used in a process when it has any WAIT statement?

1. IF
2. CASE
3. LOOP
4. Sensitivity list

✅ Correct Answer: 4

How many forms of WAIT statement are there in VHDL?

1. 1
2. 2
3. 3
4. 4

✅ Correct Answer: 3

Which of the following is not the correct WAIT statement? a) c) d)

1. WAIT ON
2. WAIT WHILE
3. WAIT FOR
4. WAIT UNTIL

✅ Correct Answer: 2

WAIT UNTIL statements cause the process to wait ________

1. When a signal changes value
2. Until a condition is true
3. For a specific time period
4. When either a signal changes its value or a condition comes true

✅ Correct Answer: 2

What is the correct syntax for using a WAIT UNTIL statement?

1. WAIT UNTIL boolean_condition_or_expression;
2. WAIT UNTIL signal_name;
3. WAIT UNTIL time_value_or_expression;
4. WAIT UNTIL boolean_expression time_value;

✅ Correct Answer: 1

What is the use of WAIT FOR statement?

1. To stop execution when the condition is false
2. To stop execution until a signal changes its value
3. To stop execution for a specific time period
4. To stop execution until the clock event occurs

✅ Correct Answer: 3

How to define a WAIT FOR statement?

1. WAIT FOR signal_name;
2. WAIT FOR booelan_expression;
3. WAIT FOR clock_event;
4. WAIT FOR time_value;

✅ Correct Answer: 4

Which of the following is the correct use of WAIT ON statement?

1. To stop execution until a signal changes its value
2. To stop execution when a signal changes its value
3. To stop execution when a condition specified is true
4. To stop execution when a condition specified is false

✅ Correct Answer: 1

Which of the following is correct syntax for WAIT ON statement?

1. WAIT ON signal_assignments;
2. WAIT ON boolean_condition;
3. WAIT ON signal_list;
4. WAIT ON time_expression;

✅ Correct Answer: 3

Which of the following statement uses only 1 signal?

1. WAIT FOR
2. WAIT UNTIL
3. WAIT ON
4. WAIT UNTIL and WAIT FOR

✅ Correct Answer: 2

Given that a process has no sensitivity list and has only one WAIT statement which is WAIT FOR statement. How many signals are there to which process is sensitive?

1. 0
2. 1
3. 2
4. Can’t be determined

✅ Correct Answer: 4

Which of the following WAIT statement is most useful for implementing a synchronous sequential circuit?

1. WAIT ON
2. WAIT FOR
3. WAIT UNTIL
4. WAIT TIME

✅ Correct Answer: 3

What is the deadlock condition in VHDL?

1. When WAIT statement keeps on waiting forever
2. When WAIT UNTIL statement uses more than one signal
3. When WAIT ON statement has only one signal
4. When WAIT FOR statement doesn’t have any time clause

✅ Correct Answer: 1

In case of sensitivity list the process suspends at the end of the process and in WAIT statement it suspends ____________

1. At the beginning
2. At the end
3. At the beginning of architecture
4. Where the WAIT statement is encountered

✅ Correct Answer: 3

In combinational logic, how many WAIT statements can be used?

1. 0
2. 1
3. 2
4. 3

✅ Correct Answer: 2

Refer to the code given below, which kind of circuit is implemented? PROCESS BEGIN WAIT on a, b; z &lt;= a AND b; END PROCESS;

1. Combinational
2. Synchronous sequential
3. Asynchronous sequential
4. State machine

✅ Correct Answer: 1

In a procedure is called from a process having a sensitivity list, how many wait statements one can use?

1. 3
2. 2
3. 1
4. 0

✅ Correct Answer: 4

Which of the following is true about WAIT UNTIL statement?

1. WAIT UNTIL statement is supported by synthesis tools
2. WAIT UNTIL statement is not supported by synthesis tools
3. WAIT UNTIL statement is supported in a clocked process only
4. WAIT UNTIL statement is supported in a combinational process

✅ Correct Answer: 3

Which of the following is true about WAIT ON statement?

1. WAIT ON statement is supported by synthesis tools
2. WAIT ON statement is not supported by synthesis tools
3. WAIT ON statement is supported in a clocked process only
4. WAIT ON statement is supported in a combinational process

✅ Correct Answer: 4

In a procedure, __________ statement is not supported.

1. WAIT UNTIL
2. WAIT ON
3. WAIT FOR
4. WAIT FOR and unconditional WAIT

✅ Correct Answer: 4

What kind of circuit is implemented by the following architecture? ARCHITECTURE my_arch OF my_design IS BEGIN PROCESS BEGIN WAIT ON clk; IF(clk = ‘1’) THEN y &lt;= x; END IF; END PROCESS; END my_arch;

1. D flip flop
2. Inverter
3. OR gate
4. Shift register

✅ Correct Answer: 1

WAIT FOR statement is useful only for _________

1. Synthesis
2. Simulation
3. Gate level implementation
4. Optimization

✅ Correct Answer: 2

A user wants to assign a signal after a wait of 20 ns. The process used has a sensitivity list. What is the possible way to achieve this?

1. By using WAIT FOR statement
2. By using AFTER clause c) d)
3. By using a separate process
4. By using WAIT ON statement

✅ Correct Answer: 3

Since WAIT statement can’t be synthesized many times, how a clock event can be detected then?

1. By using IF(clk = ‘1’)
2. By using ‘EVENT keyword
3. By using a CASE statement
4. By using a LOOP

✅ Correct Answer: 2

Which of the following can be used to make the process wait indefinitely?

1. WAIT FOR indefinite ns;
2. WAIT UNTIL false;
3. WAIT;
4. WAIT UNTIL true;

✅ Correct Answer: 3

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VHDL Mcq – WAIT Statements