For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?

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For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?

1.ISA

2.ANSA

3.Super-scalar

4.All of the mentioned

Posted Date:-2021-03-14 23:02:27

More MCQS Questions and answers

  1. ___ register Connected to the Processor bus is a single-way transfer capable.
  2. _____ are used to overcome the difference in data transfer speeds of various devices.
  3. _____ bus structure is usually used to connect I/O devices.
  4. _____ is generally used to increase the apparent size of physical memory.
  5. _____ is used to choose between incrementing the PC or performing ALU operations.
  6. ______ are numbers and encoded characters, generally used as operands.
  7. _______ is used to store data in registers.
  8.  IBM developed a bus standard for their line of computers ‘PC AT’ called _____
  9. A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______
  10. A source program is usually in _______
  11.  The ALU makes use of _______ to store the intermediate results.
  12.  The Input devices can send information to the processor.
  13.  The instruction -> Add LOCA, R0 does _______
  14.  To extend the connectivity of the processor bus we use ________
  15.  Which registers can interact with the secondary storage?
  16. An optimizing Compiler does _________
  17. ANSI stands for __________
  18. As of 2000, the reference system to find the performance of a system is _____
  19. As of 2000, the reference system to find the SPEC rating are built with _____ Processor.
  20. CISC stands for _______
  21. During the execution of a program which gets initialized first?
  22. During the execution of the instructions, a copy of the instructions is placed in the ______
  23. For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?
  24. The ______ format is usually used to store data.
  25. If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the value of S is (Where S is a term of the Basic performance equation)?
  26. In multiple Bus organisation, the registers are collectively placed and referred as ______
  27. ISP stands for _________
  28. MFC stands for ___________
  29. SPEC stands for _______
  30. The 8-bit encoding format used to store data in a computer is ______
  31. The average number of steps taken to execute the set of instructions can be made to be less than one by following _______
  32. The bus used to connect the monitor to the CPU is ______
  33. The clock rate of the processor can be improved by _________
  34. The control unit controls other units by generating ________
  35. The decoded instruction is stored in ______
  36. The I/O interface required to connect the I/O device to the bus consists of ______
  37. The internal components of the processor are connected by _______
  38. The ISA standard Buses are used to connect ________
  39. The main advantage of multiple bus organisation over a single bus is _____
  40. The main virtue for using single Bus structure is ____________
  41. The registers, ALU and the interconnection between them are collectively called as _____
  42. The small extremely fast, RAM’s are called as _______
  43. The time delay between two successive initiations of memory operation _______
  44. The ultimate goal of a compiler is to ________
  45. To reduce the memory access time we generally make use of ______
  46. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?
  47. When Performing a looping operation, the instruction gets stored in the ______
  48. Which memory device is generally made of semiconductors?
  49. Which of the register/s of the processor is/are connected to Memory Bus?
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