The CPU hardware has a wire called __________ that the CPU senses after executing every instruction.

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The CPU hardware has a wire called __________ that the CPU senses after executing every instruction.

1.interrupt request line

2. interrupt bus

3.interrupt receive line

4.interrupt sense line

Posted Date:-2022-03-26 09:32:34

More MCQS Questions and answers

  1. A character stream device transfers _____
  2. I/O is a _________ in system performance.
  3. In a real time system the computer results _______
  4. In a safety critical system, incorrect operation _____
  5. The __________ is used by device controllers to request service.
  6. What is Event latency?
  7. What is the disadvantage of real addressing mode?
  8. A ____ a set of wires and a rigidly defined protocol that specifies a set of messages that can be sent on the wires.
  9. A ________ is a collection of electronics that can operate a port, a bus, or a device.
  10. A ________ is a full duplex connection between a device driver and a user level process.
  11. A block device transfers ________
  12. A keyboard is an example of a device that is accessed through a __________ interface.
  13. A non blocking system call _________
  14. An asynchronous call ______
  15. An I/O port typically consists of four registers status, control, ________ and ________ registers.
  16. Antilock brake systems, flight management systems, pacemakers are examples of _______
  17. Buffering is done to _______
  18. Caching _____
  19. Caching is ________ spooling.
  20. Division by zero, accessing a protected or non existent memory address, or attempting to execute a privileged instruction from user mode are all categorized as ________
  21. For large data transfers, _________ is used.
  22. If one or more devices use a common set of wires to communicate with the computer system, the connection is called ______
  23. If the number of cycles spent busy – waiting is not excessive, then ____
  24. In a ______ real time system, it is guaranteed that critical real time tasks will be completed within their deadlines.
  25. In general the two interrupt request lines are _____
  26. In polling _________
  27. Interrupt latency refers to the period of time ____
  28. Preemptive, priority based scheduling guarantees _______
  29. Priority inversion is solved by use of _________
  30. Real time systems must have _______
  31. Real time systems need to __________ the interrupt latency.
  32. Some of the properties of real time systems include _____
  33. Spooling _______
  34. The ______ register is read by the host to get input.
  35. The ______ register is written by the host to send output.
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  37. The ________ keeps state information about the use of I/O components.
  38. The _________ are reserved for events such as unrecoverable memory errors.
  39. The _________ determines the cause of the interrupt, performs the necessary processing and executes a return from the interrupt instruction to return the CPU to the execution state prior to the interrupt.
  40. The _________ present a uniform device-access interface to the I/O subsystem, much as system calls provide a standard interface between the application and the operating system.
  41. The amount of memory in a real time system is generally ________
  42. The amount of time required for the scheduling dispatcher to stop one process and start another is known as _______
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  44. The hardware mechanism that allows a device to notify the CPU is called ______
  45. The interrupt vector contains _____
  46. The kernel data structures include __________
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