Bachelor of Computer Applications MCQs set-2 Computer MCQs: multiple choice questions and answers,Mock Tests and Practice Papers

Question:

A __________ gate gives the output as 1 only if all the inputs signals are 1.

1.AND

2.OR

3.EXOR

4.NOR

Posted Date:-2022-06-22 01:29:16

Question:

A NOR gate can be derived from ______

1.NAND gate

2.XOR gate

3.AND gate

4.OR gate

Posted Date:-2022-06-22 01:09:38

Question:

Conversion from prefix to postfix expression can be done _______________

1.using bubble sort

2.using radix sort

3.using two queues

4.in a direct manner

Posted Date:-2022-06-21 04:31:24

Question:

Different parameter optimization is easily achievable in

1.nMOS

2.pMOS

3.pseudo nMOS

4. CMOS

Posted Date:-2022-06-24 04:28:04

Question:

Electronic circuits that operate on one or more input signals to produce standard output _______

1.Series circuits

2.Parallel Circuits

3.Logic Signals

4.Logic Gates

Posted Date:-2022-06-22 01:28:19

Question:

Equalizing of rise time and fall time is possible in

1.nMOS

2. pseudo nMOS

3. pseudo nMOS

4.pMOS

Posted Date:-2022-06-24 04:22:44

Question:

Evaluation of 4*5+3/2-9 in prefix notation.

1.*45-/32+9

2.*+453/-29

3.-+*45/329

4.*+/45932

Posted Date:-2022-06-21 04:27:48

Question:

Evaluation of expression a/b+c*d-e in postfix notation.

1.ab+cd/*-e

2.ab/cd*+e-

3.abc/+d*-e

4.abcd/+*-e

Posted Date:-2022-06-21 04:24:33

Question:

For minimum D consider

1.Ln = Lp = 2λ

2.Ln greater than Lp = 2λ

3. Lp greater than Ln

4.Lp = 2Ln

Posted Date:-2022-06-24 04:25:37

Question:

High and low noise margins can be equalized by

1.βn = βp

2.βn greater than βp

3.βn lesser than βp

4.Lp = 2Ln

Posted Date:-2022-06-24 04:23:50

Question:

How many NAND gates are required to make an XOR gate?

1.7

2.12

3. 4

4.8

Posted Date:-2022-06-21 06:08:22

Question:

In BiCMOS inverter, the BJT used are __________

1.Only Npn BJT

2.Only Pnp BJT

3.Both npn and pnp BJT

4.Multi emitter npn BJT

Posted Date:-2022-06-24 04:12:30

Question:

In BiCMOS, the analysis of the operation of BJT is well explained by ___________

1.RC Model

2.Emitter resister model

3.Ebers Moll Model d) Hybrid model

4.Ebers Moll Model d) Hybrid model

Posted Date:-2022-06-24 04:20:15

Question:

In Boolean algebra, the data is a bit-representation of information consists of _________

1.0 and 1

2.2 and 5

3.1 and 15

4.4 and 8

Posted Date:-2022-06-21 06:06:01

Question:

In infix to postfix conversion algorithm, the operators are associated from?

1.right to left

2.left to right

3.centre to left

4.centre to right

Posted Date:-2022-06-11 22:22:04

Question:

In Multiplexer gate, for selecting the inputs, two bits named _____ and _____ are required generally.

1.selector bit, data bit

2.parity bit. Generator bit

3.input bit, inverted bit

4.raising bit, sinking bit

Posted Date:-2022-06-21 06:16:25

Question:

In OR gate for 13 numbers of inputs what are the stages possible for it?

1.1239

2.213

3.13

4.1387

Posted Date:-2022-06-22 01:07:14

Question:

In order to make a luggage security alarm, a single _____ is used.

1.NOR gate

2.NAND gate

3.X-NOR gate

4.XOR gate

Posted Date:-2022-06-21 06:04:14

Question:

In which logic gate the output state is usually the complement of the input state?

1.NOT gate

2.NOR gate

3.X-NOR gate d) OR gate

4.X-NOR gate d) OR gate

Posted Date:-2022-06-22 01:08:10

Question:

Infix to prefix conversion can be done using __________

1.two queues

2.two stacks

3.one stack and two queues

4. one stack

Posted Date:-2022-06-21 04:28:35

Question:

Inverter pair delay D is given as equal to

1.tr

2.tf

3.tr-tf

4.tr+tf

Posted Date:-2022-06-24 04:24:47

Question:

Prefix expression can be evaluated _________

1.from right to left

2.from left to right

3.from the exact middle

4.from second right element

Posted Date:-2022-06-21 06:03:07

Question:

Rise time and fall time can be also equalized by

1.Lp = Ln = λ

2.Lp = Ln = λ/2

3.Lp = Ln = 2λ

4.2Lp = Ln = λ

Posted Date:-2022-06-24 04:21:34

Question:

The BiCMOS are preferred over CMOS due to ______________

1.Switching speed is more compared to CMOS

2.Sensitivity is less with respect to the load capacitance

3.High current drive capability

4.All of the mentioned

Posted Date:-2022-06-24 04:08:33

Question:

The Bipolar Transistor is fabricated on __________

1.Same substrate of nMOS

2.N-well in p Substrate

3.P-well in n Substrate

4.Same substrate of pMOS

Posted Date:-2022-06-24 04:14:44

Question:

The boolean expression of an OR gate is _______

1.A.B

2.A’B+AB’

3.A+B

4.A’B’

Posted Date:-2022-06-22 01:30:14

Question:

The collector contact region is doped with higher concentration of n-type impurities due to __________

1.It creates a depletion region at the contact surface

2.It creates a low conductivity path between collector region and contact

3.It reduces contact resistance

4.It can withstand high voltages as compared to collector region

Posted Date:-2022-06-24 04:18:01

Question:

The expression of an EXOR gate is ____________

1.A’B+AB’

2.AB+A’B’

3.A+A.B

4.A’+B’

Posted Date:-2022-06-24 04:06:06

Question:

The gate which is called an inverter is called _________

1.NOR

2.NAND

3.EXOR

4.NOT

Posted Date:-2022-06-24 04:05:07

Question:

The gate which is used to reverse the output obtained is _____

1.NOR

2.NAND

3.EXOR

4.NOT

Posted Date:-2022-06-22 01:32:08

Question:

The high current driving capability of the BiCMOS is due to __________

1.NMOS in saturation mode

2.PMOS in saturation mode

3. CMOS

4.BJT

Posted Date:-2022-06-24 04:11:37

Question:

The n-well collector is formed by __________

1.Lightly doped n-type epitaxial layer on p-Substrate

2.Heavily doped n-type epitaxial layer on p-Substrate

3.Lightly doped n-type diffused layer on p-Substrate

4.Heavily doped n-type diffused layer on p-Substrate

Posted Date:-2022-06-24 04:17:09

Question:

The n-well created for Bipolar Transistor in BiCMOS is used as __________

1.Substrate

2.Collector

3.Emitter

4.None of the mentioned

Posted Date:-2022-06-24 04:15:49

Question:

The transistors used in BiCMOS are __________

1.BJT

2.MOSFET

3.Both BJT and MOSFETs

4. JFET

Posted Date:-2022-06-24 04:10:41

Question:

The universal gate that can be used to implement any Boolean expression is __________

1.NAND

2.EXOR

3.OR

4.AND

Posted Date:-2022-06-24 03:43:47

Question:

Using which component a shift register is implemented?

1.register

2.transistor

3.latch

4. flip-flop

Posted Date:-2022-06-21 06:07:12

Question:

What is the postfix expression of (A+B)-C*(D/E))+F?

1.A B + C D E / * – F +

2.A B C D E + / * F – +

3.A B C + * D E / F + –

4.A B + C – * D E / F +

Posted Date:-2022-06-21 05:58:52

Question:

What is the postfix expression of 9+3*5/(10-4)?

1.9 3 + * 5 / 10 4 –

2.9 3 5 + * / 10 4 –

3.9 3 + 5 * / 10 4 –

4.9 3 5 * / + 10 – 4

Posted Date:-2022-06-21 05:57:29

Question:

What is the postfix expression of the given expression, (2*4-(5+7/3^4)-8)10?

1.2 4 5 * 7 3 4 ^ / + 8 – – 10

2.2 4 * ^ 5 7 3 4 / + 8 10 – –

3.2 4 * 5 7 ^ 3 4 / + – 8 10 –

4.2 4 * 5 7 3 4 ^ / + – 8 – 10

Posted Date:-2022-06-21 06:01:09

Question:

What is the work of BJT in BiCMOS?

1.Current controlled Voltage source

2.Voltage controlled Current source

3.Current controlled current source

4.Voltage controlled current source

Posted Date:-2022-06-24 04:19:02

Question:

What should be done when a left parenthesis ‘(‘ is encountered?

1.It is ignored

2.It is placed in the output

3.It is placed in the operator stack

4.The contents of the operator stack is emptied

Posted Date:-2022-06-11 22:16:34

Question:

When logic gates are connected to form a gating/logic network it is called as a ______________ logic circuit.

1.combinational

2.sequential

3.systematic

4.hardwired

Posted Date:-2022-06-22 01:33:56

Question:

When Zp.d. or Zp.u. increases, delay

1.increases

2.decreases

3.remains the same

4. delay becomes zero

Posted Date:-2022-06-24 04:29:01

Question:

Which of the following gate will give a 0 when both of its inputs are 1?

1.AND

2.OR

3.NAND

4.EXOR

Posted Date:-2022-06-22 01:33:05

Question:

Which of the following gates is used to implement a logical conditional?

1.OR gate

2.Magnetic logic gate

3.XOR gate

4.IMPLY gate

Posted Date:-2022-06-22 01:12:28

Question:

Which of the following gates is used to implement a logical conditional?

1.OR gate

2.Magnetic logic gate

3.XOR gate

4. IMPLY gate

Posted Date:-2022-06-22 01:26:59

Question:

Which of the following is an infix expression?

1.(a+b)*(c+d)

2.ab+c*

3. +ab

4.abc+*

Posted Date:-2022-06-11 22:17:46

Question:

Which of the following is built exclusively from NOR gate?

1.Plant guard machine

2.Apollo Guidance Computer

3.Street market app

4.Dish washer

Posted Date:-2022-06-22 01:11:27

Question:

Which of the following is the drawback of the BiCMOS circuits?

1.Sensitivity is less load capacitance

2.Bipolar transistors are used for driving current to the load capacitance but not for the logic operations

3.Increased fabrication Complexity

4.All of the mentioned

Posted Date:-2022-06-24 04:13:50

Question:

Which of the following statement is incorrect with respect to infix to postfix conversion algorithm?

1.operand is always placed in the output

2.operator is placed in the stack when the stack operator has lower precedence

3.parenthesis are included in the output d) higher and equal priority operators follow the same condition

4.higher and equal priority operators follow the same condition

Posted Date:-2022-06-21 04:20:38

Posted on by R4R Team

Computer/Bachelor of Computer Applications MCQs set-2 Sample Test,Sample questions

Question: A __________ gate gives the output as 1 only if all the inputs signals are 1.

Question: A NOR gate can be derived from ______

Question: Conversion from prefix to postfix expression can be done _______________

Question: Different parameter optimization is easily achievable in

Question: Electronic circuits that operate on one or more input signals to produce standard output _______

Question: Equalizing of rise time and fall time is possible in

Question: Evaluation of 4*5+3/2-9 in prefix notation.

Question: Evaluation of expression a/b+c*d-e in postfix notation.

Question: For minimum D consider

Question: High and low noise margins can be equalized by

Question: How many NAND gates are required to make an XOR gate?

Question: In BiCMOS inverter, the BJT used are __________

Question: In BiCMOS, the analysis of the operation of BJT is well explained by ___________

Question: In Boolean algebra, the data is a bit-representation of information consists of _________

Question: In infix to postfix conversion algorithm, the operators are associated from?

Question: In Multiplexer gate, for selecting the inputs, two bits named _____ and _____ are required generally.

Question: In OR gate for 13 numbers of inputs what are the stages possible for it?

Question: In order to make a luggage security alarm, a single _____ is used.

Question: In which logic gate the output state is usually the complement of the input state?

Question: Infix to prefix conversion can be done using __________

Question: Inverter pair delay D is given as equal to

Question: Prefix expression can be evaluated _________

Question: Rise time and fall time can be also equalized by

Question: The BiCMOS are preferred over CMOS due to ______________

Question: The Bipolar Transistor is fabricated on __________

Question: The boolean expression of an OR gate is _______

Question: The collector contact region is doped with higher concentration of n-type impurities due to __________

Question: The expression of an EXOR gate is ____________

Question: The gate which is called an inverter is called _________

Question: The gate which is used to reverse the output obtained is _____

Question: The high current driving capability of the BiCMOS is due to __________

Question: The n-well collector is formed by __________

Question: The n-well created for Bipolar Transistor in BiCMOS is used as __________

Question: The transistors used in BiCMOS are __________

Question: The universal gate that can be used to implement any Boolean expression is __________

Question: Using which component a shift register is implemented?

Question: What is the postfix expression of (A+B)-C*(D/E))+F?

Question: What is the postfix expression of 9+3*5/(10-4)?

Question: What is the postfix expression of the given expression, (2*4-(5+7/3^4)-8)10?

Question: What is the work of BJT in BiCMOS?

Question: What should be done when a left parenthesis ‘(‘ is encountered?

Question: When logic gates are connected to form a gating/logic network it is called as a ______________ logic circuit.

Question: When Zp.d. or Zp.u. increases, delay

Question: Which of the following gate will give a 0 when both of its inputs are 1?

Question: Which of the following gates is used to implement a logical conditional?

Question: Which of the following gates is used to implement a logical conditional?

Question: Which of the following is an infix expression?

Question: Which of the following is built exclusively from NOR gate?

Question: Which of the following is the drawback of the BiCMOS circuits?

Question: Which of the following statement is incorrect with respect to infix to postfix conversion algorithm?

More MCQS

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Question:
A __________ gate gives the output as 1 only if all the inputs signals are 1.

Question:
A NOR gate can be derived from ______

Question:
Conversion from prefix to postfix expression can be done _______________

Question:
Different parameter optimization is easily achievable in

Question:
Electronic circuits that operate on one or more input signals to produce standard output _______

Question:
Equalizing of rise time and fall time is possible in

Question:
Evaluation of 4*5+3/2-9 in prefix notation.

Question:
Evaluation of expression a/b+c*d-e in postfix notation.

Question:
For minimum D consider

Question:
High and low noise margins can be equalized by

Question:
How many NAND gates are required to make an XOR gate?

Question:
In BiCMOS inverter, the BJT used are __________

Question:
In BiCMOS, the analysis of the operation of BJT is well explained by ___________

Question:
In Boolean algebra, the data is a bit-representation of information consists of _________

Question:
In infix to postfix conversion algorithm, the operators are associated from?

Question:
In Multiplexer gate, for selecting the inputs, two bits named _ and _ are required generally.

Question:
In OR gate for 13 numbers of inputs what are the stages possible for it?

Question:
In order to make a luggage security alarm, a single _____ is used.

Question:
In which logic gate the output state is usually the complement of the input state?

Question:
Infix to prefix conversion can be done using __________

Question:
Inverter pair delay D is given as equal to

Question:
Prefix expression can be evaluated _________

Question:
Rise time and fall time can be also equalized by

Question:
The BiCMOS are preferred over CMOS due to ______________

Question:
The Bipolar Transistor is fabricated on __________

Question:
The boolean expression of an OR gate is _______

Question:
The collector contact region is doped with higher concentration of n-type impurities due to __________

Question:
The expression of an EXOR gate is ____________

Question:
The gate which is called an inverter is called _________

Question:
The gate which is used to reverse the output obtained is _____

Question:
The high current driving capability of the BiCMOS is due to __________

Question:
The n-well collector is formed by __________

Question:
The n-well created for Bipolar Transistor in BiCMOS is used as __________

Question:
The transistors used in BiCMOS are __________

Question:
The universal gate that can be used to implement any Boolean expression is __________

Question:
Using which component a shift register is implemented?

Question:
What is the postfix expression of (A+B)-C*(D/E))+F?

Question:
What is the postfix expression of 9+3*5/(10-4)?

Question:
What is the postfix expression of the given expression, (2*4-(5+7/3^4)-8)10?

Question:
What is the work of BJT in BiCMOS?

Question:
What should be done when a left parenthesis ‘(‘ is encountered?

Question:
When logic gates are connected to form a gating/logic network it is called as a ______________ logic circuit.

Question:
When Zp.d. or Zp.u. increases, delay

Question:
Which of the following gate will give a 0 when both of its inputs are 1?

Question:
Which of the following gates is used to implement a logical conditional?

Question:
Which of the following gates is used to implement a logical conditional?

Question:
Which of the following is an infix expression?

Question:
Which of the following is built exclusively from NOR gate?

Question:
Which of the following is the drawback of the BiCMOS circuits?

Question:
Which of the following statement is incorrect with respect to infix to postfix conversion algorithm?