VHDL/VHDL Mcq – Signal vs Variables Sample Test,Sample questions

Question:
 The process of transforming a design entry information of the circuit into a set of logic equations in any EDA tool is known as _________

1.Simulation

2.Synthesis

3.Optimization

4.Verification

Posted Date:-2022-02-09 12:29:29


Question:
 What is the advantage of using VHDL instead of any other HDL?

1.Week typing

2.Based on ADA

3.Portability

4.Easy to code

Posted Date:-2022-02-09 16:00:54


Question:
 Which of the following is a characteristic of VHDL?

1. Case sensitive

2.Use of simple data types

3.Based on C programming language

4.Strongly typed language

Posted Date:-2022-02-09 16:02:14


Question:
 Which of the following is not a back end EDA tool?

1.Floor planning tools

2.Placement tools

3.Routing tools

4.Simulators

Posted Date:-2022-02-09 15:51:16


Question:
 Which of the following is the default mode for a port variable?

1.IN

2.OUT

3.INOUT

4.BUFFER

Posted Date:-2022-02-09 18:46:59


Question:
 Which of the following mode of the signal is bidirectional?

1.IN

2.OUT

3.INOUT

4.BUFFER

Posted Date:-2022-02-09 18:29:07


Question:
A constant is declared in Architecture, it will be accessible in ________

1.Whole code

2.Within the same architecture

3.In the entity associated and corresponding architecture

4.In the process within the architecture

Posted Date:-2022-02-09 12:19:10


Question:
A user wants a constant to be declared in such a way that it can be accessible by whole code, where should the user declare this constant?

1.Package

2.Entity

3.Architecture

4.Configuration

Posted Date:-2022-02-09 12:22:24


Question:
After compiling VHDL code with any EDA tool, we get __________

1.Final device

2.FPGA

3.Optimized netlist

4.Netlist

Posted Date:-2022-02-09 12:26:23


Question:
An Antifuse programming technology is associated with _________

1.CPLDs

2.FPGAs

3.SPLDs

4.ASICs

Posted Date:-2022-02-09 12:30:17


Question:
How to control the structure and timing of the entity can be changed?

1.By using TIME variable in the entity

2.By changing the entity declaration from time to time

3.By using some special code

4.By using GENERICS

Posted Date:-2022-02-09 18:41:23


Question:
How to declare a constant in VHDL?

1.CONSTANT name : type := value;

2.CONSTANT name := value;

3.CONSTANT name := type := value;

4.CONSTANT name := type : value;

Posted Date:-2022-02-09 12:17:26


Question:
In an assignment statement, OUT signal can be used only to the ___________

1.Left of <= operator

2.Right of <= operator

3.Any side of <= operator

4.Right of := operator

Posted Date:-2022-02-09 18:29:54


Question:
n what aspect, HDLs differ from other computer programming languages?

1.No aspect; both are same

2.HDLs describe hardware rather than executing a program on a computer

3.HDLs describe software and not hardware

4.Other computer programming languages have more complexity

Posted Date:-2022-02-09 15:56:55


Question:
On which side of assignment operator, we can use the IN type signal?

1.Left

2.Right

3.Both

4.Can’t be used

Posted Date:-2022-02-09 18:30:36


Question:
Use of constants is to _________

1.Represent wires

2.Represent local information

3.Represent default value

4.Pass value between entities

Posted Date:-2022-02-09 12:16:37


Question:
VHDL is based on which of the following programming languages?

1.ADA programming language

2.C

3.Assembly

4.PHP

Posted Date:-2022-02-09 16:00:11


Question:
What are the differences between simulation tools and synthesis tool?

1.Simulators are used to check the performance of circuit and Synthesis tools are for the fabrication of circuits

2.Simulators and Synthesis tools works exactly same

3.Simulators are used just to check basic functionality of the circuit and Synthesis tools includes timing constraints and other factors along with simulation

4.Simulation finds the error in the code and Synthesis tool corrects the code

Posted Date:-2022-02-09 15:52:18


Question:
What is the basic use of EDA tools?

1. Communication of Electronic devices

2.Fabrication of Electronics hardware

3. Electronic circuits simulation and synthesis

4.Industrial automation

Posted Date:-2022-02-09 12:25:42


Question:
What is the difference between OUT and BUFFER?

1.BUFFER can’t be used inside the entity for reading the value and OUT can be

2.BUFFER can only be read whereas OUT can only be assigned a value c)

3.BUFFER can be read as well as assigned a value but OUT can only be assigned

4.Both are same

Posted Date:-2022-02-09 18:37:01


Question:
What is the difference between OUT and BUFFER?

1.BUFFER can’t be used inside the entity for reading the value and OU can be

2.BUFFER can only be read whereas OUT can only be assigned a value c) BUFFER can be read as well as assigned a value but OUT can only be assigned

3.Both are same

4.Both are same

Posted Date:-2022-02-09 18:40:11


Question:
What is the extension of the netlist file; input to the place and route EDA tools?

1.EIDF

2.SDF

3.TXT

4.CPP

Posted Date:-2022-02-09 15:54:00


Question:
What is the full form of VHDL?

1.Verilog Hardware Description Language

2.Very High speed Description Language

3.Variable Hardware Description Language

4.Very high speed Hardware Description Language

Posted Date:-2022-02-09 12:24:41


Question:
What is the scope of a constant declared in an entity?

1.Local to the entity

2.Global to the whole code

3.Local to the port

4.Global to the entity and all the architecture associated

Posted Date:-2022-02-09 12:21:07


Question:
What is the use of a variable?

1.To represent local value

2.To represent default value

3.To set default value

4.To declare a subprogram

Posted Date:-2022-02-09 12:15:57


Question:
Which of the following can be the name of an entity?

1.NAND

2.Nand_gate

3.Nand gate

4.AND

Posted Date:-2022-02-09 18:24:21


Question:
Which of the following can’t be declared in an architecture?

1.Signal

2.Constant

3.Variable

4.BIT_VECTOR

Posted Date:-2022-02-09 12:20:17


Question:
Which of the following HDLs are IEEE standards?

1.VHDL and Verilog

2.C and C++

3.Altera and Xilinx

4.Quartus II and MaxPlus II

Posted Date:-2022-02-09 15:57:41


Question:
Which of the following is a characteristic of Verilog HDL?

1.Strongly typed language

2.Case sensitive

3.Better library

4. Not portable

Posted Date:-2022-02-09 16:04:30


Question:
Which of the following is local to the block in which it is declared?

1.Signal

2.Integer

3.Constant

4.Variable

Posted Date:-2022-02-09 12:18:02


Question:
Which of the following is not an EDA tool?

1.Visual C++

2.Quartus II

3.Xilinx ISE

4.MaxPlus II

Posted Date:-2022-02-09 12:28:42


Question:
Which of the following is not defined by the entity?

1.Direction of any signal

2.Names of signal

3.Different ports

4. Behavior of the signals

Posted Date:-2022-02-09 18:23:21


Question:
Which of the following is the correct use of the signal?

1. To set a default value

2.To pass value between circuits

3.To declare a variable

4.To represent local information

Posted Date:-2022-02-09 12:15:00


Question:
Which of the following is used at the end of a statement?

1.; (Semicolon)

2.— ( double hyphen)

3._ (underscore)

4.No sign is used at the end of statement

Posted Date:-2022-02-09 18:19:19


Question:
Which of the following is used at the end of a statement?

1.; (Semicolon)

2.— ( double hyphen)

3._ (underscore)

4.No sign is used at the end of statement

Posted Date:-2022-02-09 18:21:24


Question:
Why do we need concurrent processing for describing digital systems in HDLs?

1.Faster processing than conventional programming languages

2.Concurrent processing is easier than sequential processing

3.It allows taking timing constraints into consideration

4.Complexity of digital systems needs concurrent processing

Posted Date:-2022-02-09 15:59:28


Question:
Why we needed HDLs while having many traditional Programming languages?

1.Traditional programming languages are complex

2.HDLs are complementary to traditional programming languages to complete the design process

3.Some characteristics of digital hardware couldn’t be captured by traditional languages

4.HDLs offer more complexity than traditional programming languages.

Posted Date:-2022-02-09 15:58:32


More MCQS

  1. Introduction to VHDL Mcq
  2. VHDL Mcq – Data Objects and Types
  3. VHDL Mcq– Behavioural Modelling
  4. VHDL Mcq – Structural Modeling
  5. VHDL Mcq – Types of VHDL Modelling
  6. VHDL Mcq – WAIT Statements
  7. VHDL Mcq – Signal vs Variables
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