VHDL/VHDL Mcq – Types of VHDL Modelling Sample Test,Sample questions

Question:
 If a user gets an error at the time of simulation which is “ the IF statement is illegal” what could be the reason?

1.Using IF statement in architecture body

2.Using IF statement without ELSE

3.Using multiple ELSE statements

4.Using concurrent assignment in the IF

Posted Date:-2022-02-09 10:52:27


Question:
 If one wants to perform no action, when any condition is true, then which of the following keyword can be used?

1.NO OPERATION;

2.NOP;

3.NULL;

4.NEXT

Posted Date:-2022-02-09 11:10:35


Question:
 In a clocked process, IF statement is used to __________

1.To run statements sequentially

2.To use concurrent assignment within process

3.To detect the clock signal

4.To implement sequential circuit

Posted Date:-2022-02-09 10:53:15


Question:
 In case any of the conditions is not covered by ‘cases’ in the case statement, which of the following keyword can be used to cover all those conditions?

1.ELSE

2.ELSIF

3.REMAINING

4.OTHERS

Posted Date:-2022-02-09 11:02:21


Question:
 In the following lines, what should be the value of signal y, if a and b both are at logic high?

PROCESS (a, b)
BEGIN
IF( a XOR b <=’1’)
y <= ‘1’;
ELSIF (a AND b <= ‘0’)
y &lt;= a;
ELSE
y &lt;= ‘0’;
END IF;
END PROCESS;

1.a

2.b

3.0

4.1

Posted Date:-2022-02-09 10:49:09


Question:
 It is not possible to use range with _________ types.

1.Integer

2.BIT_VECTOR

3.STD_LOGIC

4.Natural

Posted Date:-2022-02-09 11:11:14


Question:
 On what side of the assignment statement, one can use a loop index?

1.Left

2.Right

3.Left or Right

4.Loop index can’t be used in an assignment

Posted Date:-2022-02-09 11:33:32


Question:
 The correct syntax for using EXIT in a loop is ___________

1.EXIT loop_label WHEN condition;

2. EXIT WHEN condition loop_label;

3.loop_label WHEN condition EXIT

4.EXIT WHEN loop_label condition

Posted Date:-2022-02-09 11:28:15


Question:
 The driver(s) of signal y is _________

PROCESS ()
BEGIN
y &lt;= ‘1’;
y &lt;= x;
y &lt;= z;
END PROCESS;

1.z

2.x

3.x and z

4.1

Posted Date:-2022-02-09 10:43:59


Question:
 The FOR loop is not synthesizable if it contains ______ statement.

1.WHEN

2.THEN

3.WAIT

4.IF

Posted Date:-2022-02-09 11:36:07


Question:
 The FOR loop is not synthesizable if it contains ______ statement.
a) 
d) 

1.WHEN

2.THEN

3.WAIT

4.IF

Posted Date:-2022-02-09 11:36:06


Question:
 What does modeling type refer to?

1.Type of ports in entity block of VHDL code

2.Type of description statements in architecture block of VHDL code

3.Type of data objects

4.Type of Signals

Posted Date:-2022-02-09 07:30:56


Question:
 Where do we declare the loop index of a FOR LOOP?

1.Entity

2.Architecture

3.Library

4.It doesn’t have to be declared

Posted Date:-2022-02-09 11:31:29


Question:
 Which of the following architecture defines the data flow modeling of ‘and’ gate?

1.ARCHITECTURE and_1 OF and_gate IS begin y <= a AND b; end and_1;

2.ARCHITECTURE dataflow OF and_gate IS Process(a, b, y); begin y <= a AND b; end dataflow;

3.ARCHITECTURE and_1 OF and_gate IS begin IF(a = ‘1’ and b = ‘1’) THEN c <= 1; ELSE c &lt;= ‘0’; end and_1;

4.ARCHITECTURE dataflow OF and_gate IS begin y <= a AND b; end and_1;

Posted Date:-2022-02-09 07:47:19


Question:
 Which of the following condition has topmost priority?

1.IF

2.ELSIF

3.ELSE

4.THEN

Posted Date:-2022-02-09 10:49:49


Question:
 Which of the following is a keyword used for conditional assignment?

1. IF

2.WHEN

3.FOR

4.END

Posted Date:-2022-02-09 10:10:57


Question:
 Which of the following is a variable assignment statement?

1.<=

2. :=

3.=>

4.==

Posted Date:-2022-02-09 10:10:17


Question:
 Which of the following keyword is not associated with IF statement?

1.ELSE

2.THEN

3.ELSIF

4.WHEN

Posted Date:-2022-02-09 10:46:34


Question:
 Which of the following modeling style follows the sequential processing of instructions?

1.Dataflow modeling

2.Behavior modeling

3.Structural modeling

4.Component modeling

Posted Date:-2022-02-09 07:42:09


Question:
 Which of the following statements can be seen as sequential equivalent to the selected concurrent assignment?

1.IF ELSE

2.WAIT

3.WHEN

4.CASE

Posted Date:-2022-02-09 10:21:47


Question:
A combinational process must have all the _________ signals in its sensitivity list.

1. Input

2.Output

3.Declared

4.Used

Posted Date:-2022-02-09 10:40:36


Question:
A FOR loop is inside a WHILE loop. Inside the FOR loop, the EXIT statement is used in such a way that after 4 iterations, it will execute. After the execution of EXIT statement, the control will be passed ________

1.Outside the FOR loop

2.Outside the WHILE loop

3. At the next iteration of WHILE loop

4.At the next iteration of FOR loop

Posted Date:-2022-02-09 11:32:31


Question:
A loop statement is used where we needs to ________

1.Select one from many choices

2.Check a condition

3.Repeat the statements

4.Choose one from two cases

Posted Date:-2022-02-09 11:19:02


Question:
A postponed process runs when ___________

1.All the other processes have completed

2.After completion of one particular process

3.Concurrently with all other processes

4.First of all processes

Posted Date:-2022-02-09 10:24:17


Question:
A __________ can’t be declared inside a process.

1.Signal

2.Variable

3.Constants

4.Subprograms

Posted Date:-2022-02-09 10:22:30


Question:
CASE is a sequential statement, which is similar to _________ concurrent statement.

1.Concurrent assignment

2.PORT MAP

3.WHEN

4.THEN

Posted Date:-2022-02-09 11:04:06


Question:
Delays are generally ignored in ________ assignments statements.

1.Concurrent

2.Conditional

3.Sequential

4.Selected

Posted Date:-2022-02-09 10:08:43


Question:
For a signal used in sequential assignment, it can have _______ 

1.1

2.2

3.3

4.4

Posted Date:-2022-02-09 10:11:29


Question:
FOR loop uses a loop index, the type of loop index is _________

1.STD_LOGIC_VECTOR

2.BIT_VECTOR

3.INTEGER

4.REAL

Posted Date:-2022-02-09 11:29:44


Question:
How can we use an assignment statement as a sequential assignment?

1.By using keyword WAIT

2.By using a delay mechanism

3.By using conditional statements

4.By using it in any process

Posted Date:-2022-02-09 08:14:55


Question:
If no signal in the sensitivity list is changed, then how many times the process will be executed?

1. 3

2.2

3.1

4.0

Posted Date:-2022-02-09 10:21:07


Question:
If the condition of IF statement is an expression, then what should be the type of the result of the expression?

1.Bit

2.Std_logic

3.Boolean

4.Integer

Posted Date:-2022-02-09 10:48:15


Question:
If there is more than one process in a VHDL code, How they are executed?

1.One after the other

2.Concurrently

3.According to sensitivity list

4.Sequentially

Posted Date:-2022-02-09 10:16:38


Question:
In behavioral modeling, what do descriptive statements describe?

1.How the system performs on given input values

2.How e design is to be implemented

3.Netlist

4.Concurrent execution

Posted Date:-2022-02-09 07:38:32


Question:
In behavioral modeling, what do descriptive statements describe?

1. How the system performs on given input values

2.How e design is to be implemented

3.Netlist

4.Concurrent execution

Posted Date:-2022-02-09 07:39:27


Question:
In which of the following statements, all the branches are equal in priority?

1. IF

2.CASE

3.WAIT

4.LOOP

Posted Date:-2022-02-09 11:01:03


Question:
Local variables in a process can be declared __________

1.Anywhere within the process

2.After a sequential statement

3.Before the BEGIN keyword

4.After the BEGIN keyword

Posted Date:-2022-02-09 10:17:31


Question:
Loop is a ________ statement.

1.Concurrent

2.Sequential

3.Assignment

4.Functional

Posted Date:-2022-02-09 11:19:45


Question:
One IF statement can have multiple ___________

1. IF

2.ELSIF

3.ELSE

4.CASE

Posted Date:-2022-02-09 10:51:32


Question:
Ports are known as _________ to the component.

1.Structure

2.Behavior

3.Function

4.Interface

Posted Date:-2022-02-09 07:53:53


Question:
Process is a _______ statement.

1.Concurrent

2.Sequential

3.Delay

4.Both concurrent and sequential

Posted Date:-2022-02-09 10:15:14


Question:
Refer to the code given below, what kind of circuit is designed?

SIGNAL x : IN BIT;
SIGNAL y : OUT BIT;
SIGNAL clk : IN BIT;
PROCESS (clk)
BEGIN
IF (clk’EVENT and clk = ‘1’)
y ;&lt= x;
END PROCESS

1.Buffer

2.Latch

3.Flip flop

4.Shift Register

Posted Date:-2022-02-09 10:43:11


Question:
Refer to the code given below, which type of modeling is used to describe the system?

ARCHITECTURE and_1 OF and_gate IS
begin
process(a, b, y)
begin
IF(a = ‘1’ and b = ‘1’) THEN
y <= ‘1’;
ELSE y <=’0’;
end IF;
END process;
END and_1;

1.Structural

2.Component

3.Dataflow

4.Behavioral

Posted Date:-2022-02-09 07:49:17


Question:
Sensitivity list of a process contains __________

1.Constants

2.Signals

3.Variables

4.Literals

Posted Date:-2022-02-09 10:18:47


Question:
The CASE statement in VHDL is similar to _________ in C.

1.Switch

2.If else

3.Pointers

4.Arrays

Posted Date:-2022-02-09 11:12:06


Question:
The concurrent assignment statement is activated whenever ______

1.The execution is scheduled

2.The value of the target is needed

3.The waveform associated changes its value

4.The process is terminated

Posted Date:-2022-02-09 09:37:12


Question:
The concurrent assignment statement is activated whenever ______

1.The execution is scheduled

2.The value of the target is needed

3.The waveform associated changes its value

4.The process is terminated

Posted Date:-2022-02-09 09:40:02


Question:
The conditional assignment statement is a _________ assignment.

1.Sequential

2.Concurrent

3.Selected

4.None of the above

Posted Date:-2022-02-09 10:02:23


Question:
The conditional assignment statement is a _________ assignment.

1.Sequential

2.Concurrent

3.Selected

4.None of the above

Posted Date:-2022-02-09 10:07:47


Question:
The process can be __________ by using WAIT statements.

1.Suspended

2.Resumed

3.Suspended as well as resumed

4.Cannot be determined

Posted Date:-2022-02-09 10:23:32


Question:
The resolution function is needed to resolve the value of _______

PROCESS ()
BEGIN
y &lt;= x;
y &lt;= z;
END PROCESS;

1.z

2.y

3. x

4.No x, y and z

Posted Date:-2022-02-09 10:44:46


Question:
The selected concurrent statement is equivalent to ________ sequential statement.

1.If else

2.Loop

3.Wait

4.Case

Posted Date:-2022-02-09 10:12:35


Question:
The sequential assignment statement is activated, whenever ________

1.The waveform associated changes its value

2.The process is terminated

3.The execution is scheduled

4.The value of the target is needed

Posted Date:-2022-02-09 09:35:09


Question:
The signal assignment is considered as a ________

1.Concurrent statement

2.Sequential statement

3.Subprogram

4.Package declaration statement

Posted Date:-2022-02-09 08:13:34


Question:
The value of y is initially 1 and it is changed after one delta cycle to 0. How many delta cycles (starting from the beginning) will be taken to change the initial value of z, refer to the process given below?

PROCESS (y)
BEGIN
x &lt;=y;
z &lt;= NOT y;
END PROCESS

1.1

2.2

3.3

4.4

Posted Date:-2022-02-09 10:27:39


Question:
Those statement which are placed under ________ are concurrent.

1.Process

2.Function

3.Architecture

4.Procedure

Posted Date:-2022-02-09 10:14:16


Question:
What does the next statement in loops do?

1.Skips the current iteration

2.Starts the next loop by ending the current

3.Exits the loop

4.Skips the next line of the loop

Posted Date:-2022-02-09 11:25:27


Question:
What is the basic unit of behavioral description?

1.Structure

2.Sequence

3.Process

4.Dataflow

Posted Date:-2022-02-09 07:41:15


Question:
What is the effect of the sensitivity list on the process?

1. Process executes when any of the signal in sensitivity list changes

2.Process executes sequentially when sensitivity list is specified

3. If there is no sensitivity list, then the process will not execute

4.Helps in simulation

Posted Date:-2022-02-09 10:20:24


Question:
What is the main use of a CASE statement?

1.To design multiplexers

2.To design Comparators

3.To design Flip flop

4.To design state machines

Posted Date:-2022-02-09 11:13:50


Question:
What is the problem with IF statement?

1.Overlapping of conditions

2.No default value

3.The condition can be Boolean only

4.Restriction on number of ELSE statement

Posted Date:-2022-02-09 10:56:28


Question:
What is the syntax to use the NEXT statement?

1.NEXT condition loop_label

2.NEXT loop_label WHEN condition

3.loop_label NEXT WHEN condition

4. loop_label NEXT condition

Posted Date:-2022-02-09 11:26:21


Question:
What is the use of a function called port map()?

1.Component declaration

2.Defining identifiers

3.Component instantiation

4.Defining inputs and outputs

Posted Date:-2022-02-09 07:54:47


Question:
What is the use of FOR loop?

1.To repeat the statement finite number of times

2.To repeat the statement until any condition holds true

3.To repeat the statements for infinite time

4.To repeat statements inside until any condition is false

Posted Date:-2022-02-09 11:20:25


Question:
What is the use of WHILE loop?

1.To repeat the statement finite number of times

2.To repeat the statement until any condition holds true

3.To repeat the statements for infinite time

4.To repeat statements inside until any condition is false

Posted Date:-2022-02-09 11:24:30


Question:
What kind of statement is the IF statement?

1.Concurrent

2.Sequential

3.Assignment

4.Selected assignment

Posted Date:-2022-02-09 10:45:39


Question:
What logic is described in the following logic?

PROCESS (a, b)
IF (a = ‘1’ AND b = ‘0’ OR a= ’0’ AND b = ‘1’) THEN
y &lt;= ‘1’;
ELSIF (a = ‘1’ AND b= ‘1’) THEN
y &lt;= ‘0’;
ELSE
 y &lt;= ‘0’;
END IF

1.EXOR

2.EXNOR

3.AND

4.NOR

Posted Date:-2022-02-09 10:50:42


Question:
What should be the type of choices in the CASE statement?

1.Boolean

2.Integer

3.Same as expression

4.No restriction on the type

Posted Date:-2022-02-09 11:08:15


Question:
What will be the output in the following code?

ARCHITECTURE my_logic OF my_design IS
BEGIN
a &lt;= 1;
b &lt;= 1;
PROCESS (a, b)
BEGIN
IF (a AND b = 1) THEN
output &lt;= a;
ELSIF (a OR b = 1) THEN
output &lt;= b;
ELSE
output &lt;= 0;
END IF;
END PROCESS;
END my_logic;

1.0

2.1

3.b

4.a

Posted Date:-2022-02-09 10:54:07


Question:
What will be the value of Z in the following code?

ENTITY case_1 IS
Port (a, b, c, y : IN INTEGER range 0 TO 31
           z              : OUT INTEGER range 0 TO 31)
ARCHITECTURE example OF case_1 IS
BEGIN
y &lt;= 2;
a &lt;= 4;
b &lt;= 5;
c &lt;=6;
PROCESS(a, b, c, y)
BEGIN
CASE y+1 IS
WHEN 1 =&gt;
z &lt;= a;
WHEN 2 =&gt;
z &lt;= b;
WHEN 3 =&gt;
z &lt;= c;
WHEN OTHERS =&gt;
Z &lt;= 0;
END CASE;
END PROCESS;
END example;

1.2

2.4

3.5

4.6

Posted Date:-2022-02-09 11:07:02


Question:
Which logic function is described in the code given below?

ARCHITECTURE my_func OF my_logic IS
begin
process(a, b, y)
begin
IF(a = ‘0’ and b = ‘0’) THEN
y <= ‘0’;
ELSIF (a = ‘1’ and b= ‘1’) THEN
y<= ‘0’;
ELSE y <= ‘1’;
END if;
END process;
END my_func;

1.AND

2.EXOR

3.OR

4.EXNOR

Posted Date:-2022-02-09 07:52:04


Question:
Which modeling style does the following code represents?

Architecture my_logic OF logic_func IS
Component gate_1
PORT (b1, b2 : IN BIT;
s : OUT BIT);
END component;
Component gate_2 IS
PORT (b1,b2 : IN BIT;
C : OUT BIT);
END component;
SIGNAL a, b, sum, carry : BIT;
begin
EXOR : gate_1 portmap (a, b, sum);
AND : gate_2 portmap (a,b ,carry);
END my_logic

1.Structural

2.Component

3.Behavior

4.Dataflow

Posted Date:-2022-02-09 07:53:01


Question:
Which of the following can’t be a mode for target operand of assignment statement?

1.BUFFER

2.INOUT

3.OUT

4.IN

Posted Date:-2022-02-09 10:09:36


Question:
Which of the following circuit can’t be described without using a process statement?

1.Multiplexer

2.D flip-flop

3.Decoder

4.Comparator

Posted Date:-2022-02-09 10:41:39


Question:
Which of the following is correct syntax for a signal assignment statement (if {} specifies an optional part)?

1.target <= {delay_mechanism} waveform;

2. target <= delay_mechanism waveform;

3.target <= delay_mechanism {waveform};

4.target <= {delay_mechanism} {waveform} value;

Posted Date:-2022-02-09 09:53:35


Question:
Which of the following is most complex?

1.IF THEN ELSE

2.Nested IF THEN ELSE

3.ELSIF

4.CASE

Posted Date:-2022-02-09 11:15:31


Question:
Which of the following is not a legal statement used Ii CASE?

1.WHEN 1 =>

2.WHEN 1 TO 3 =>

3.WHEN 1|3 =>

4.WHEN 1 THEN

Posted Date:-2022-02-09 11:17:10


Question:
Which of the following is not a type of VHDL modeling?

1.Behavioral modeling

2.Dataflow modeling

3.Structural modeling

4.Component modeling

Posted Date:-2022-02-09 07:33:23


Question:
Which of the following operators can’t be used in the choices of a CASE?

1.Arithmetic

2.Logical

3.Relational

4. Every type of operators can be used

Posted Date:-2022-02-09 11:13:03


Question:
Which of the following represents the correct order for keywords?

1.IF, THEN, ELSIF, THEN, ELSE

2. IF, ELSE, THEN, ELSIF, THEN

3.IF, ELSIF, THEN, ELSE, THEN

4. IF, THEN, ELSE, THEN, ELSIF

Posted Date:-2022-02-09 10:47:22


Question:
Which of the following signal uses keyword EVENT?

1.Variables

2.Output

3.Input

4.Clock

Posted Date:-2022-02-09 10:42:24


Question:
Which of the following statement can’t be used inside a process?

1.WAIT

2.IF ELSE

3.Variable declaration

4.PORT MAP

Posted Date:-2022-02-09 10:26:38


Question:
Which of the following statement is used in structural modeling?

1.portmap()

2.process()

3.if-else

4.case

Posted Date:-2022-02-09 07:40:08


Question:
Which of the following statement is used when there are no signals in the sensitive list?

1.WHEN

2.IF ELSE

3.WAIT

4.CASE

Posted Date:-2022-02-09 10:19:32


Question:
_________ modeling uses logic gates and basic blocks to describe the functionality of system.

1.Behavioral

2.Structural

3.Dataflow

4.Component

Posted Date:-2022-02-09 07:44:31


More MCQS

  1. Introduction to VHDL Mcq
  2. VHDL Mcq – Data Objects and Types
  3. VHDL Mcq– Behavioural Modelling
  4. VHDL Mcq – Structural Modeling
  5. VHDL Mcq – Types of VHDL Modelling
  6. VHDL Mcq – WAIT Statements
  7. VHDL Mcq – Signal vs Variables
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