VHDL/VHDL Mcq – Structural Modeling Sample Test,Sample questions

Question:
 In which part of the VHDL code, components must be declared?

1.Library

2.Entity

3.Architecture

4.Configuration

Posted Date:-2022-02-09 07:18:58


Question:
 Which of the following is the correct order for a structural model in VHDL?

1.Libraries, Entity declaration, Component declaration, Component instantiation

2.Libraries, Component declaration, Entity declaration, Component instantiation

3.Libraries, Entity declaration, Component instantiation, Component declaration

4.Component declaration, Libraries, Entity declaration, Component instantiation

Posted Date:-2022-02-09 07:25:52


Question:
 Which of the following is the right way to leave a port unconnected?

1.L1 : my_component PORT MAP(a); a <= OPEN;

2.L1 : my_component PORT MAP(a := OPEN);

3.L1: my_component PORT MAP(a => OPEN);

4.L1 : my_component PORT MAP(a); a := OPEN;

Posted Date:-2022-02-09 07:23:03


Question:
 __________ mapping is less error prone.

1.Port

2.Positional

3.Nominal

4.Generic

Posted Date:-2022-02-09 07:21:32


Question:
A component has 3 ports- two inputs(a and b) and one output(y). Which of the following statement is for the positional mapping of the component?

1.LABEL : my_component PORT MAP (l, m, n);

2.LABEL : my_component PORT MAP (y, a);

3.LABEL : my_component PORT MAP (l => a, m => b, n => y);

4.LABEL : my_component PORT MAP(a, b, y>= a);

Posted Date:-2022-02-09 07:22:13


Question:
How many ways are there in VHDL to map the components?

1.1

2.2

3.3

4.4

Posted Date:-2022-02-09 07:20:12


Question:
How to declare a 2 input OR gate in the structural modeling?

1.COMPONENT or IS PORT ( a, b : IN BIT; x, y : OUT BIT); END COMPONENT;

2.COMPONENT or IS PORT ( a, b : IN BIT; y : OUT BIT); END COMPONENT;

3.COMPONENT or_gate IS PORT ( a, b : IN BIT; x, y : OUT BIT); END COMPONENT;

4.COMPONENT or_gate IS PORT ( a, b : IN BIT; y : OUT BIT); END COMPONENT;

Posted Date:-2022-02-09 07:24:31


Question:
Refer to the model given below, which circuit is designed?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, x);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, y);
END arch1;

1.Half adder

2.Comparator 2- bits

3.Full adder

4. Can’t be determined

Posted Date:-2022-02-09 07:26:48


Question:
What is the property of Positional mapping?

1.Easier to write

2. Less error prone

3.Ports can be left unconnected

4.Difficult to write

Posted Date:-2022-02-09 07:20:54


Question:
Which of the following function is used to map the component?

1.COMPONENT INSTANTIATE

2.PORT MAP

3.GENERIC MAP

4.USE

Posted Date:-2022-02-09 07:19:39


More MCQS

  1. Introduction to VHDL Mcq
  2. VHDL Mcq – Data Objects and Types
  3. VHDL Mcq– Behavioural Modelling
  4. VHDL Mcq – Structural Modeling
  5. VHDL Mcq – Types of VHDL Modelling
  6. VHDL Mcq – WAIT Statements
  7. VHDL Mcq – Signal vs Variables
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