VHDL/VHDL Mcq – Data Objects and Types Sample Test,Sample questions

Question:
 If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is?

1.x <= a.b

2. x <= a OR b

3.x <= a + b

4. x <= a && b

Posted Date:-2022-02-08 13:11:48


Question:
 If we are using conv_integer(p) function, then which of the following cannot be the type of parameter ‘p’?

1.STD_LOGIC VECTOR

2.STD_ULOGIC

3.INTEGER

4.SIGNED

Posted Date:-2022-02-08 15:46:25


Question:
 In a statement containing two or more operators of same precedence, how the expression will be solved?

1.Left to right

2.Right to left

3.Alphabetically

4.In a random manner

Posted Date:-2022-02-08 17:58:04


Question:
 Look at the following declarations:

TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 ); 
TYPE array 2 IS ARRAY ( 0 TO 3 ) OF array1;
How many total bits can be stored in these arrays?

1.16

2.9

3.64

4.27

Posted Date:-2022-02-08 15:13:44


Question:
 SIGNAL x : STD_LOGIC; In this statement x is ______

1.Variable

2.Identifier

3.Name

4.Literal

Posted Date:-2022-02-08 17:49:17


Question:
 What is the correct method to declare a SIGNED type signal ‘x’?

1.SIGNAL x : IN SIGNED

2.SIGNAL x : IN SIGNED

3.SIGNAL x : IN SIGNED (7 DOWNTO 0)

4.SIGNAL x : IN SIGNED_VECTOR (7 DOWNTO 0)

Posted Date:-2022-02-08 13:05:11


Question:
 What will be the value of x in the following code?

SIGNAL x : IN UNSIGNED (3 DOWNTO 0 );
x <= “1101”;

1.12

2.5

3. -5

4.14

Posted Date:-2022-02-08 13:06:49


Question:
 What will be the value of x in the following code?

SIGNAL x : IN UNSIGNED (3 DOWNTO 0 );
x <= “1101”;

1.12

2.5

3. -5

4.14

Posted Date:-2022-02-08 13:09:16


Question:
 Which of the following is a wrong declaration for a new data type?

1.TYPE my_logic IS RANGE 0 to 100;

2.TYPE my_logic IS (‘0’, ‘1’, ‘2’);

3.TYPE my_logic IS ARRAY (0 TO 3) OF BIT;

4.TYPE my_logic IS <0 TO 20 >

Posted Date:-2022-02-08 15:08:46


Question:
. In the following statements, y and z are equivalent to________

y <= NOT a AND b;
z <= NOT (a AND b);

1. y <= a’+b’ and z <= (a.b)’

2. y <= (a+b)’ and z <= a’+b’

3.y <= a’+b and z <= a’+b’

4.y <= a+b’ and z <= a.b

Posted Date:-2022-02-08 15:55:51


Question:
. In the VHDL code given below, what will be the values of y and z?

VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001;
VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000;
VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000;
…
y := x ROR 2;
z := y ROL 2;
…

1. y = 0100 and z = 0000

2. y = 0000 and z = 0000

3.y = 0111 and z = 1110

4.y = 0110 and z = 0110

Posted Date:-2022-02-08 17:57:17


Question:
A SUBTYPE can be defined as _________

1.A TYPE under a TYPE (nested)

2.A type of INTEGER datatype

3.A TYPE with some constraint

4.A TYPE without any constraint

Posted Date:-2022-02-08 15:09:54


Question:
A VARIABLE y is declared of STD_LOGIC_VECTOR type of 4 bits, if you want to assign 1001 to y, then what is the write assignment statement?

1.y <= “1001”

2.y := “1001”

3.y <= ‘1’, ‘0’, ‘0’, ‘1’

4.y => “1001”

Posted Date:-2022-02-08 15:53:37


Question:
ABS operator is used to _________

1.Shift the operand

2.Gives absolute value for the operand

3.Give the result as nearest integer

4.To synthesize the result

Posted Date:-2022-02-08 17:46:50


Question:
Access types are similar to _________ in traditional programming languages.

1.Pointers

2.Arrays

3.Structures

4.Files

Posted Date:-2022-02-08 15:05:36


Question:
How the keyword “TYPE” is used?

1.TYPE datatype_name IS type_from_predefined_datatypes;

2.TYPE datatype_name IS datatype_range;

3.TYPE datatype_range IS datatype_name;

4.USE TYPE datatype_range IS datatype_name;

Posted Date:-2022-02-08 15:06:45


Question:
In the following VHDL code, the values of y and z are _____

VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001;
VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000;
VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000;
…
y := x SRA 2;
z := y SLA 2;
…

1.y = 0000 and z = 0000

2.y = 1001 and z = 0000

3.y = 1110 and z = 0111

4.y = 0111 and z = 1110

Posted Date:-2022-02-08 17:54:40


Question:
In the function conv_unsigned(p, b), what does p and b refers to?

1.p is the data object to be converted and b is the base of that data object

2.p is the data object to be converted amd b is the bits needed in converted variable

3.p is the parameter to be converted and b is the bits of same parameter

4.p is the type of data to be converted and b is the type of data into which p should be converted

Posted Date:-2022-02-08 15:47:18


Question:
In the VHDL code given below, what will be the error at the time of compilation?

TYPE my_int IS INTEGER RANGE -32 TO 32;
TYPE other_int IS INTEGER RANGE 0 TO 100;
SIGNAL x : my_int;
SIGNAL y : other_int;
y <= x + 2;

1.Type mismatch

2.Syntax problem

3.No declaration

4.Can’t compile

Posted Date:-2022-02-08 15:28:42


Question:
RECORD in VHDL is similar to________ in C.

1.Array

2.File

3.Structure

4.Pointer

Posted Date:-2022-02-08 15:04:10


Question:
Refer to the four declarations below, which of the following is not a 2 dimensional array?

TYPE array1 IS ARRAY ( 3 DOWNTO 0, 1 DOWNTO 0 ) OF STD_LOGIC;
TYPE array2 IS ARRAY (3 DOWNTO 0 ) OF STD_LOGIC_VECTOR( 3 DOWNTO 0 );
TYPE array3 IS ARRAY (2 DOWNTO 0 )  OF array2;
TYPE array4 IS ARRAY ( 0 TO 3, 3 DOWNTO 0 ) OF BIT;

1.array4

2.array3

3.array2

4.array1

Posted Date:-2022-02-08 15:14:50


Question:
Refer to the VHDL code given below, which of the following line has error?

Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’;
Line 2: SIGNAL a: BIT;
Line 3: SIGNAL b: STD_LOGIC;
Line 4: SIGNAL c: my_logic;
Line 5: b<=a;
Line 6: b<=c;

1.Line 1

2. Line 4

3. Line 5

4. Line 6

Posted Date:-2022-02-08 15:17:30


Question:
SIGNAL a : REAL; which of the following is illegal assignment for a?

1.a <= 1.8

2.a <= 1.0 E10

3.a <= 1.0 E-10

4.a <=1.0 ns

Posted Date:-2022-02-08 15:02:39


Question:
SIGNED and UNSIGNED data types are defined in which package?

1.std_logic_1164 package

2.std_logic package

3.std_logic_arith package

4.standard package

Posted Date:-2022-02-08 13:04:19


Question:
SLL operation is equivalent to which of the following operations?

1.Multiplication by any natural number

2.Multiplication by 2

3.Division by 2

4.Exponential operation

Posted Date:-2022-02-08 17:55:28


Question:
The correct syntax for any logical shift operator like SLL and SRL is_____

1.bit_vector_operand <OPERATOR> integer_operand

2.integer_operand <OPERATOR> bit_vector_operand

3.std_logic_operand <OPERATOR> integer_operand

4. integer_operand <OPERATOR> std_logic_operand

Posted Date:-2022-02-08 17:53:16


Question:
The function conv_std_logic_vector(p,b) is used for_______

1.Converting ‘p’ form STD_LOGIC_VECTOR to STD_LOGIC type

2.Converting any data type ‘p’ into STD_LOGIC_VECTOR with ‘b’ bits

3.Converting STD_LOGIC_VECTOR into ‘p’ type with ‘b’ bits

4.Converting STD_LOGIC into STD_LOGIC_VECTOR

Posted Date:-2022-02-08 15:49:22


Question:
The operator ‘&’ is called the_____ operator.

1.Logical AND operator

2.Bitwise AND operator

3.Arithmetic addition operator

4.Concatenation operator

Posted Date:-2022-02-08 16:01:02


Question:
The operators like =, /=, <, >, >= are called _________

1.Arithmetic operators

2.Concatenation operators

3.Logical operators

4.Relational operators

Posted Date:-2022-02-08 16:02:59


Question:
What do we call the data type used for representing distance, current, voltage, time, etc?

1.Integer

2.Real

3.Physical

4.Imaginary

Posted Date:-2022-02-08 14:59:41


Question:
What is the “SLL” operator?

1.Shift Logic Left

2. Shift Logically

3.Shift Left Logical

4.Shift Left

Posted Date:-2022-02-08 17:50:08


Question:
What is the “SLL” operator?

1.Shift Logic Left

2.Shift Logically

3.Shift Left Logical

4.Shift Left

Posted Date:-2022-02-08 17:52:20


Question:
What is the difference between SIGNAL and VARIABLE?

1.The value of SIGNAL never varies whereas VARIABLE can change its value

2.SIGNAL can be used for input or output whereas VARIABLE acts as intermediate signals

3.SIGNAL depends upon VARIABLE for various operations

4.SIGNAL is global and VARIABLE is local to the process in which it is declared

Posted Date:-2022-02-08 15:04:57


Question:
What is the meaning of the base unit?

1.Smallest possible unit of any physical literal

2.SI unit of any physical literal

3.CGS unit for any physical literal

4. Fundamental building block of any design

Posted Date:-2022-02-08 15:00:50


Question:
What is the type of result for comparison operators?

1.Boolean

2.Integer

3.Numeric

4.Array

Posted Date:-2022-02-08 16:03:50


Question:
What is the type of result of MOD operator?

1.Numeric

2.Integer

3.Array

4.Bit

Posted Date:-2022-02-08 16:02:04


Question:
What will be the value of y after the execution of the following VHDL code?

Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
…
SIGNAL m : UNSIGNED (3 DOWNTO 0);
SIGNAL n : UNSIGNED (3 DOWNTO 0);
SIGNAL y : STD_LOGIC_VECTOR (7 DOWNTO 0);
y <=CONV_STD_LOGIC_VECTOR ((m+n), 8);

1.8- bit STD_LOGIC_VECTOR m+n

2.8- bit UNSIGNED m+n

3.4- bit STD_LOGIC m+n

4.Error

Posted Date:-2022-02-08 15:50:37


Question:
What will be the values of following variables after REM operations?

x = 5 REM 3;
y = -5 REM 3;
z = 5 REM -3;

1.x= 2, y = 1 and z = -2

2.x = 2, y = -2 and z = 1

3.x = 2, y = -2 and z = 2

4. x = 2, y = 1 and z = 1

Posted Date:-2022-02-09 05:06:34


Question:
What will be the values of the following variables after MOD operations?

x = 5 MOD 3;
y = -5 MOD 3;
z = 5 MOD -3;

1.x = 2, y = -2 and z = -2

2.x = 2, y = 1 and z = -2

3.x= 2, y = -2 and z = 2

4.x = 2, y = -2 and z = 1

Posted Date:-2022-02-08 17:59:02


Question:
Which of the following can’t be the value of x? Refer to the VHDL code given below.

TYPE color IS (red, green, blue, black, white, gray);
SUBTYPE primary IS color RANGE red to blue;
VARIABLE x: primary;

1.White

2.Red

3.Green

4.Blue

Posted Date:-2022-02-08 15:12:32


Question:
Which of the following is a SUBTYPE of INTEGER?

1.NATURAL

2.REAL

3.CHARACTER

4.STD_LOGIC

Posted Date:-2022-02-08 15:15:36


Question:
Which of the following is equivalent division by 2 operator?

1.SRL

2.SLL

3.SLA

4.SRA

Posted Date:-2022-02-08 17:56:22


Question:
Which of the following is exponentiation operator?

1.^

2.*

3./=

4.**

Posted Date:-2022-02-08 17:47:48


Question:
Which of the following is not an assignment operator?

1.<=

2.:=

3.=>

4.=

Posted Date:-2022-02-08 15:52:23


Question:
Which of the following is only predefined physical literal in VHDL?

1.VOLTAGE

2.TIME

3.CURRENT

4.DISTANCE

Posted Date:-2022-02-08 15:01:49


Question:
Which of the following is the correct syntax for declaring a SUBTYPE?

1.TYPE type_name IS type_range AND SUBTYPE subtype_name IS subtype_range

2.SUBTYPE subtype_name IS subtype_range TYPE type_name

3.SUBTYPE subtype_name TYPE type_name IS subtype_range

4.SUBTYPE subtype_name IS TYPE subtype_range

Posted Date:-2022-02-08 15:10:56


Question:
Which of the following is the correct syntax to convert INTEGER ‘p’ into SIGNED number of ‘b’ bits?

1.conv_integer_signed(p,b);

2.conv_signed_integer(p,b);

3.conv_signed(p,b);

4.conv_signed_p(b);

Posted Date:-2022-02-08 15:48:19


Question:
Which of the following logical operator has the highest precedence?

1.NAND

2.NOR

3.NOT

4.EXOR

Posted Date:-2022-02-08 15:54:31


Question:
Which of the following option is completely legal, given that a and b are two UNSIGNED type signals?

1.x <= a + b; y <= a – b;

2.x <= a OR b; y <= a AND b;

3.x <= a + b; y <= a OR b;

4.x <= a OR b; y <= a + b;

Posted Date:-2022-02-08 13:10:08


Question:
Which of the following package of IEEE contains most of the data conversion functions?

1.std_logic_1164

2.std

3.std_logic_arith

4.std_logic

Posted Date:-2022-02-08 15:44:11


Question:
Which of the following VHDL statement is equivalent to NAND operation, if y, a and b are SIGNALS?

1. y <= NOT a AND b

2. y <= NOT a OR NOT b

3.y <<= NOT a AND NOT b

4.y <<= NOT (a OR b)

Posted Date:-2022-02-08 15:56:33


Question:
_____ operator is unary as well as binary operator.
a) 

1.–

2.*

3./

4.**

Posted Date:-2022-02-08 15:57:20


More MCQS

  1. Introduction to VHDL Mcq
  2. VHDL Mcq – Data Objects and Types
  3. VHDL Mcq– Behavioural Modelling
  4. VHDL Mcq – Structural Modeling
  5. VHDL Mcq – Types of VHDL Modelling
  6. VHDL Mcq – WAIT Statements
  7. VHDL Mcq – Signal vs Variables
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